# GammaCORE UCIe Die-to-Die Controller IP

GammaCORE is a highly configurable and customizable Universal Chiplet Interconnect Express (UCle™) Die-to-Die Controller IP implementing the latest UCIe 2.0 specification and supporting UCIe Streaming protocol applications.

With Alphawave’s [AresCORE D2D PHY IP](https://awavesemi.com/silicon-ip/phy-ip/die-to-die-phy-ip/), GammaCORE provides the complete UCIe solution for an open and robust chiplet ecosystem.​

## GammaCORE UCIe Die-to-Die (D2D) Controller IP

GammaCORE UCIe D2D Controller IP enables multi-die applications, such as the connection of I/O chiplets to a main die, accelerator die to a processor die, multi-die packet processors, multi-die Ethernet switches, etc. ​

GammaCORE Controller IP core consists of the Streaming Protocol Layer, to extend the SoC interface across the UCIe link, and the Adapter Layer, to provide a reliable end-to-end link. ​

On the UCIe link side, GammaCORE provides seamless connection to the [AresCORE UCIe](https://awavesemi.com/silicon-ip/phy-ip/die-to-die-phy-ip/) D2D PHY IP through the RDI interface. On the system side, GammaCORE connects to one or multiple internal SoC interfaces.

### High Configurability and Customizability​

GammaCORE supports ​

- Any specific SOC Interface: AXI4, AXI-S, TileLink, CXS, CHI, and some proprietary interfaces over UCIe. ​
- Flit and Raw mode operation.​
- Configurable datapath width to address specific Bandwidth and target clock frequency requirements.​
- Combination with other Alphawave Semi companion IP cores to enable many different configurations.

### Comprehensive Verification

The GammaCORE Controller IP has been verified against leading UCIe Verification IPs (VIP). The IP is silicon-proven, together with Alphawave’s AresCORE UCIe D2D PHY, on variety of test chips in leading-edge foundries across multiple technology nodes.

#### Typical Applications

The AresCORE UCIe D2D interconnect enables SoC developers to break the boundaries of the reticle limit by including multiple dies in the same package. This multi-die approach to silicon design allows for better yielding, smaller purposeful dies vs. traditional SoCs. The main target applications AresCORE UCIe D2D interconnect include, but are not limited to:

- AI accelerators
- Server class CPUs
- Network switches designed for large compute
- FPGAs
- 5G base stations
- IO and optical transceivers

#### Additional Resources

1. **Press Releases:**
   - [Alphawave Semi Scales UCIe™ to 64 Gbps Enabling >20 Tbps/mm Bandwidth Density for Die-to-Die Chiplet Connectivity](https://awavesemi.com/press-release/alphawave-semi-scales-ucie-to-64-gbps-enabling-20-tbps-mm-bandwidth-density-for-die-to-die-chiplet-connectivity/)
   - [Unveiling the Industry’s First Silicon-Proven 3nm, 24Gbps UCIe™ IP Subsystem with TSMC CoWoS® Technology](https://awavesemi.com/press-release/unveiling-the-industrys-first-silicon-proven-3nm-24gbps-ucie-ip-subsystem-with-tsmc-cowos-technology/)
   - [Alphawave Semi Drives Innovation in Hyperscale AI Accelerators with Advanced I/O Chiplet for Rebellions Inc.](https://awavesemi.com/press-release/alphawave-semi-drives-innovation-in-hyperscale-ai-accelerators-with-advanced-i-o-chiplet-for-rebellions-inc/)
   - [Alphawave Semi Tapes Out Industry-First, Multi-Protocol I/O Connectivity Chiplet for High-Performance Compute and AI Infrastructure](https://awavesemi.com/press-release/alphawave-semi-tapes-out-industry-first-multi-protocol-i-o-connectivity-chiplet-for-high-performance-compute-and-ai-infrastructure/)
   - [Alphawave Semi Collaborates with Arm on High-Performance Compute Chiplet](https://awavesemi.com/press-release/alphawave-semi-collaborates-with-arm-on-high-performance-compute-chiplet/)
   - [Alphawave Semi Demonstrates 3nm Silicon-Proven 24Gbps Universal Chiplet Express™ (UCIe™) Subsystem for High-Performance AI Infrastructure](https://awavesemi.com/press-release/alphawave-semi-demonstrates-3nm-silicon-proven-24gbps-universal-chiplet-express-ucie-subsystem-for-high-performance-ai-infrastructure/)
   - [Alphawave Semi Spearheads Chiplet-Based Custom Silicon for Generative AI and Data Center Workloads with Successful 3nm Tapeouts of HBM3 and UCIe IP](https://awavesemi.com/press-release/alphawave-semi-spearheads-chiplet-based-custom-silicon-for-generative-ai-and-data-center-workloads-with-successful-3nm-tapeouts-of-hbm3-and-ucie-ip/)
   - [Alphawave Semi Elevates Chiplet-Powered Silicon Platforms for AI Compute through Arm Total Design](https://awavesemi.com/press-release/alphawave-semi-elevates-chiplet-powered-silicon-platforms-for-ai-compute-through-arm-total-design/)
2. **On-Demand Videos:**
   - [Building the Future: Next-Generation Terabit AI Networks with the Industry’s First Multi-Protocol I/O Connectivity Chiplet](https://awavesemi.com/resource/building-the-future-next-generation-terabit-ai-networks-with-the-industrys-first-multi-protocol-i-o-connectivity-chiplet/)
   - [From Simulation to Silicon: Alphawave & Keysight’s UCIe Validation at DAC 2024 – Video](https://awavesemi.com/resource/from-simulation-to-silicon-alphawave-keysights-ucie-validation-at-dac-2024-video/)
   - [Achieving High Performance Compute with AI Chiplets Through UCIe Die-to-Die Interconnects](https://awavesemi.com/resource/achieving-high-performance-compute-with-ai-chiplets-through-ucie-die-to-die-interconnects-webinar/)