# UCIe Die-to-Die (D2D) IP Subsystem

Alphawave’s UCIe Die-to-Die IP Subsystem offers a unique solution with extremely low power, high throughput, and low latency links enabling faster time to integration for heterogenous chiplet connections in wired communications, Artificial Intelligence (AI), High Performance Computing (HPC), Datacenters and Networking applications.​

## UCIe D2D IP Subsystem

UCIe D2D IP Subsystem is targeted for heterogeneous chiplet solutions. With recent advances in package technologies, it is possible to route high-speed signals within a package connecting multiple dies either on an interposer or on an organic substrate. Alphawave’s UCIe D2D IP Subsystem offers a complete solution with AresCORE UCIe D2D PHY and GammaCORE UCIe D2D controller IPs to enable faster time to integration.​

### AresCORE UCIe D2D PHY IP

- High bandwidth density per mm of shoreline, >21 Tbps/mm (Advanced Package) and >3.5 Tbps/mm (Standard Package)​
- High data-rate-per-lane, up to 64 Gbps​
- Extremely power efficient with less than 0.35 pJ/bit power consumption​
- Channel lengths support up to 5mm with latency less than 2ns (Other combinations are available)​
- Built-in PLL to support differential clock forwarding​
- Equipped with full calibrations, training, DFT, and reliability features​
- Comprehensive testability with Built-In Self-Test (BIST), internal and external loopback, and non-destructive eye diagram​
- Features for KGD (Known Good Die) testing​
- Complete set of test vehicles for interoperability testing for robust chiplet ecosystem​
- Available in leading-edge foundries across multiple technology nodes

[Learn More](https://awavesemi.com/silicon-ip/phy-ip/die-to-die-phy-ip/)

### GammaCORE UCIe D2D Controller IP

- Highly configurable and customizable Controller IP with Streaming Protocol Layer, to extend the SoC interface across the UCIe link, and the Adapter Layer, to provide a reliable end-to-end link​
- Adapter (CRC/Retry) based on 256B Latency Optimized Flit format​
- Streaming protocol for any specific SOC Interface: AXI4, AXI-S, TileLink, CXS, CHI, and some proprietary interfaces over UCIe​
- Supports both Flit and Raw mode operation ​
- Optional clock domain crossing between SoC and UCIe controller clocks​
- Configurable datapath width to address specific bandwidth and target clock frequency requirements​
- Flexible and scalable:
  - any channel width​
  - any number of channels per port
  - any number of ports (multi-ported configs)
- Can be combined with other Alphawave Semi companion IP cores to enable many different configurations

[Learn More](https://awavesemi.com/silicon-ip/controller-ip/ucie-d2d-controller/)

#### Additional Resources

1. **Press Releases:**
   - [Alphawave Semi Scales UCIe™ to 64 Gbps Enabling >20 Tbps/mm Bandwidth Density for Die-to-Die Chiplet Connectivity](https://awavesemi.com/press-release/alphawave-semi-scales-ucie-to-64-gbps-enabling-20-tbps-mm-bandwidth-density-for-die-to-die-chiplet-connectivity/)
   - [Unveiling the Industry’s First Silicon-Proven 3nm, 24Gbps UCIe™ IP Subsystem with TSMC CoWoS® Technology](https://awavesemi.com/press-release/unveiling-the-industrys-first-silicon-proven-3nm-24gbps-ucie-ip-subsystem-with-tsmc-cowos-technology/)
   - [Alphawave Semi Drives Innovation in Hyperscale AI Accelerators with Advanced I/O Chiplet for Rebellions Inc.](https://awavesemi.com/press-release/alphawave-semi-drives-innovation-in-hyperscale-ai-accelerators-with-advanced-i-o-chiplet-for-rebellions-inc/)
   - [Alphawave Semi Tapes Out Industry-First, Multi-Protocol I/O Connectivity Chiplet for High-Performance Compute and AI Infrastructure](https://awavesemi.com/press-release/alphawave-semi-tapes-out-industry-first-multi-protocol-i-o-connectivity-chiplet-for-high-performance-compute-and-ai-infrastructure/)
   - [Alphawave Semi Collaborates with Arm on High-Performance Compute Chiplet](https://awavesemi.com/press-release/alphawave-semi-collaborates-with-arm-on-high-performance-compute-chiplet/)
   - [Alphawave Semi Demonstrates 3nm Silicon-Proven 24Gbps Universal Chiplet Express™ (UCIe™) Subsystem for High-Performance AI Infrastructure](https://awavesemi.com/press-release/alphawave-semi-demonstrates-3nm-silicon-proven-24gbps-universal-chiplet-express-ucie-subsystem-for-high-performance-ai-infrastructure/)
   - [Alphawave Semi Spearheads Chiplet-Based Custom Silicon for Generative AI and Data Center Workloads with Successful 3nm Tapeouts of HBM3 and UCIe IP](https://awavesemi.com/press-release/alphawave-semi-spearheads-chiplet-based-custom-silicon-for-generative-ai-and-data-center-workloads-with-successful-3nm-tapeouts-of-hbm3-and-ucie-ip/)
   - [Alphawave Semi Elevates Chiplet-Powered Silicon Platforms for AI Compute through Arm Total Design](https://awavesemi.com/press-release/alphawave-semi-elevates-chiplet-powered-silicon-platforms-for-ai-compute-through-arm-total-design/)
2. **On-Demand Videos:**
   - [Building the Future: Next-Generation Terabit AI Networks with the Industry’s First Multi-Protocol I/O Connectivity Chiplet](https://awavesemi.com/resource/building-the-future-next-generation-terabit-ai-networks-with-the-industrys-first-multi-protocol-i-o-connectivity-chiplet/)
   - [From Simulation to Silicon: Alphawave & Keysight’s UCIe Validation at DAC 2024 – Video](https://awavesemi.com/resource/from-simulation-to-silicon-alphawave-keysights-ucie-validation-at-dac-2024-video/)
   - [Achieving High Performance Compute with AI Chiplets Through UCIe Die-to-Die Interconnects](https://awavesemi.com/resource/achieving-high-performance-compute-with-ai-chiplets-through-ucie-die-to-die-interconnects-webinar/)

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